1. Technical Field
This disclosure is generally related to power converters, and is more particularly related to regulated power converters.
2. Description of the Related Art
Power converters are used in both alternating current (AC) input and direct current (DC) input applications where energy storage is required for hold-up and filtering in both normal and power-fail circumstances. In such applications, multi-stage conversion often provides a desirable power architecture. One example is a power architecture that uses multi-stage conversion providing several outputs on sub-3.3VDC output rails. Such a power architecture is particularly useful in systems having multiple circuit card assemblies (multi-CCA) of moderate to high power (e.g., about 200 W to 2 KW and higher). In such multi-CCA systems, an initial power stage converts source AC or DC power to an intermediate DC voltage, typically 5 VDC, 12 VDC, 28 VDC, or 48 VDC, which is distributed to the CCAs through a backplane or interconnecting cable, and one or more final stages of conversion local to each CCA to convert the intermediate voltage to the low voltage(s) required.
Many applications require power supplies having a plurality of outputs. For example, computing based applications utilize power supplies that can deliver a number of distinct voltage outputs. One example of this type of multi-output power supply architecture is used in a computing server system. An example of such power supply architecture is shown in the computing server 101 of FIG. 1A.
FIG. 1A illustrates a known computing server 101. An alternating current (AC) source is input to an initial rectifier circuit 104 of a main power supply 103. The output of the rectifier circuit 104 is input to a boost stage 107. The output of the boost stage 107 is coupled to a first DC-to-DC power supply 108, a second DC-to-DC power supply 111, and to an energy storage circuit 113. In the known computing server embodiment 101 of FIG. 1A, the main power supply 103 provides two outputs for the computing server 101. A first output, produced by the first DC-to-DC power supply 108, is a 5V standby voltage. A second output, produced by the second DC-to-DC power supply 111, is a 12V supply voltage. The 12V supply voltage in the embodiment of FIG. 1A is used to supply several power distribution circuits of the computing server 101.
A first power distribution circuit 114 includes a voltage regulator VRA. The first power distribution circuit 114 receives a 12V input from the second DC-to-DC converter 111 of the main power supply 103, and produces a regulated voltage output A. Additional power distribution circuits VRB, VRF, VRH, and VRI also receive the 12V input from the second DC-to-DC converter 111 of the main power supply 103. The power distribution circuits VRB, VRF, VRH, and VRI produce regulated voltage outputs B, F, H, and I respectively.
Another set of power distribution circuits VRC, VRD, and VRE receive at their inputs respectively the regulated output voltage I from power distribution circuit VRI. The power distribution circuits VRC, VRD, and VRE produce regulated voltage outputs C, D, and E respectively. One additional power distribution circuit VRA receives regulated voltage output F from VRF and produces further regulated voltage output G.
The distributed power circuits illustrated in FIG. 1A show an intermediate bus architecture wherein a main power supply 103 produces a system voltage signal for distribution via an intermediate bus 109. The intermediate bus 109 carries the common system voltage signal to multiple individual power distribution circuits that can each be physically located very close to their energy consuming loads. For example, power distribution circuit VRA can be physically located very close to a first processor 132. The close proximity of a power distribution circuit to its energy consuming load helps to reduce energy losses that occur over longer transmission paths of low voltage, high current power signals.
Table 1 identifies particular operating parameters of the power distribution circuits VRA-VRI. The operating parameters represent one embodiment of the known power architecture of computing server 101 in FIG. 1A.
TABLE 1PowerDistributionOperatingOutputCircuitEfficiencyInputVoltageCurrentDynamic transientVRA80%12 VDC0.95~1.7V100A100A/μsecVRB80%12 VDC0.95~1.7V100A100A/μsecVRC86%VRI1.5V6A1A/nsecVRD85%VRI1.2V7.2A1A/nsecVRE26%VRI1.3V0.5A1A/nsecVRF86%12 VDC1.8V0.65A0.025A/nsecVRG85%VRF0.9VVRH96%12 VDC3.3V0.24A0.36A/nsecVRI96%12 VDC5V
The known computing server 101 of FIG. 1A also includes several conventional server elements. First and second processors 132, 134 respectively execute firmware and/or software instructions to configure and implement the operations of the computing server 101. A chipset 136 includes one or more peripherals of the server such as video rendering circuits, communication ports, clock generation, and the like.
A memory 138 in the computing server 101 includes any volatile and non-volatile electronic storage media as may be used by the server. For example, non-volatile memory, such as flash memory or the like, is useful for storing configuration settings, calibration settings, clock timing information, program instructions, and other information that persists through a power-cycle operation of the computing server 101. Volatile memory, such as random access memory (RAM), is useful for quickly storing and retrieving operating data used by one or more of the processors 132, 134. A hard disk drive (HDD) 140 in computing server 101 is conventionally used for storing program instructions and data.
A final element of the known computing server 101 captures other functions 142 found in conventional computing servers. For example, some servers add particular peripherals for control and use by the processors 132, 134. In some cases, the other functions 142 include audio input/output devices, security devices, data input device controllers such as keyboards, mice, track pads, touch screens, and many others.
As is evident in the computing server 101 of FIG. 1A, the power distribution circuits 114-130 are operable to provide a range of power values for distribution in the computing server 101. Shown in one embodiment, the first processor 132 receives regulated voltage outputs A, D, and H. The second processor 134 receives regulated voltage outputs B, D, and H. Chipset 136 receives regulated voltage outputs C, D, F, E, and H. Memory receives inputs F and G and HDD receives a 12V source from the second DC-to-DC converter 111 and regulated voltage output I. The other circuits 142 receive the 12V source from DC-to-DC converter 111 and regulated voltage inputs H and I.
Table 2 identifies particular operating inputs to the elements of the computing server 101. The operating inputs represent one embodiment of the power architecture of computing server 101 in FIG. 1A.
TABLE 2ComputingOutputServerDynamicComponentInputVoltageCurrenttransientProcessor 1VRA0.95~1.7V100A100A/μsecVRD1.2V7.2A1A/nsecVRH3.3V30mAProcessor 2VRB0.95~1.7V100A100A/μsecVRD1.2V7.2A1A/nsecVRH3.3V30mAChipsetVRC1.5V6A1A/nsecVRD1.2V7.2A1A/nsecVRF1.8V0.65A0.025A/nsecVRE1.3V0.5A1A/nsecVRH3.3V0.24A0.36A/nsecMemoryVRF1.8V0.65A0.025A/nsecVRG0.9VHDDDC-to-12VDCDCVRI5VOtherDC-to-12VDCDCVRI5VVRH3.3V0.24A0.36A/nsec
Many circuits of the computing server 101 should remain operational during dropouts or loss of the input source. Often, when a dropout is a short term event (e.g., less than 200 ms), the ability to continue powering the circuits is accommodated by capacitive energy storage and associated circuitry. Long term tolerance to a loss of input may be provided by other sources such as a battery, and in these applications some internal capacitive energy storage can assist in providing smooth source transitions.
In conventional systems, the output of the first boost stage 107 is regulated during normal operation. The first boost stage 107 output represents the highest operating voltage of the DC-to-DC power converter 111 that follows. When the input source to the first boost stage 107 is lost, however, the first boost stage 107 isolates the energy storage circuit 113 from the input line, and the energy storage circuit 113 becomes the source input to the DC-to-DC power converter 111. As the DC-to-DC power converter 111 draws energy, the voltage of the energy storage circuit 113 declines. The length of time over which the entire power architecture can maintain a regulated output voltage is proportional to both the capacitive value of the energy storage circuit 113 and the input voltage range of the DC-to-DC power converter 111.
In the computing server 101 of FIG. 1A, energy storage circuit 113 provides an output capacitance for the first boost stage 107. Generally, the energy storage circuit 113 is a single capacitor. The output capacitance of the energy storage circuit 113 is generally sized as a function of the energy required to meet the design parameters for hold-up when the input source supply is lost. A similar function is also used to size the output capacitance of other commonly used solutions for DC input converters with particular hold-up requirements.
During the hold-up interval, i.e., when the input voltage source is lost, the energy storage circuit 113 voltage will decay. That is, since the energy storage circuit 113 is no longer sourced via the boost stage 107, and since the energy storage circuit 113 further continues to supply the second DC-to-DC converter 111, the charge in the energy storage circuit 113 will begin to be released.